Involved in the miniaturization of LSIs, wiring is also miniaturized much progressively. Copper to be used as a wiring material at present is approaching its limit of the withstanding current density in the wiring miniaturization, and it is expected to employ a new material for wiring. A carbon nanotube (CNT) has a high current density and is easily grown on a nanoscale. Therefore, a CNT is one of the materials which are regarded as a next-generation wiring material.
There have been several manufacturing methods for CNT via wiring. One of the conventional methods is to provide the CNT via wiring by growing CNTs only in via holes to be described with reference to FIGS. 4A and 5C.
FIGS. 4A to 4F are views showing manufacturing steps of the CNT via wiring according to one of the conventional methods As shown in the figures, it is structured such that a lower wiring layer (first wiring layer) 2 is formed in a semiconductor substrate 1 including semiconductor devices such as a transistor or a capacitor, and an interlayer insulating film 3 having a via hole 11 is formed thereon to connect the lower wiring layer 2 to an upper electrode 9. The first step to the step to form the via hole 11 are not fundamentally different from conventional LSI wiring steps. After the via hole 11 is formed in the interlayer insulating film 3, a metal barrier layer 4, e.g., a tantalum nitride (TaN) layer is formed. Next, catalyst layers 5, 6 which are important for growing CNTs, such as titanium nitride (TiN) or cobalt (Co), are formed sequentially. In growing CNTs, it is possible to use only one catalyst layer 6 (FIG. 4A).
Next, in order to grow CNTs only inside the via hole, the catalyst layers in a region except the via hole (here, called a “field region” of the substrate) are removed (FIG. 4B). In order to remove the catalyst layers from the field region, argon (Ar) ion oblique milling is carried out. Next, CNTs are grown using a plasma CVD method. In this case, the catalyst layers are removed from the field region as shown in FIG. 4C, thereby allowing it to grow CNTs 7 only inside the via hole 11. After the growth of CNTs 7, it is possible to flatten the surface of the substrate having multiwalled carbon nanotubes (MW (multiwalled) CNTs) to make the inner layers (graphen sheets) of the MWCNTs 7 contribute to electric conduction. In case that the upper electrode is formed directly on MWCNTs 7, only the outermost CNT layers contribute to the conduction as shown in FIG. 6A (“closed ends”) In such a case, the CNTs 7 cannot serve sufficiently as via wiring. Consequently, chemical mechanical polishing (CMP) is performed on the entire substrate to entirely flatten the substrate for “open ends” of MWCNTs 7.
That is, the tip portions of MWCNTs 7 are also cut with CMP, and an upper electrode is formed on the MWCNTs 7 whose tip portions are cut. Thereby, the inner CNT layers (graphen sheets) of MWCNTs 7 can also contribute to the conduction to electrically connect the upper and lower electrodes to each other, as shown in FIG. 6B (“open ends”). In the conventional example, before performing CMP, an embedded film 8 is formed in the via hole shown in FIG. 4D to fix MWCNTs 7 included in the via hole 11. Silicon oxide (SiO2 series) films, such as SOG (Spin On Glass), are used for the embedded film 8. After performing CMP (FIG. 4E), the upper electrode 9 is formed as shown in FIG. 4F.
The above-described is the manufacturing process of CNT via wiring according to the conventional example. When the via wiring is manufactured according to the manufacturing process mentioned above, the embedded film 8 shown in FIG. 4D is not uniformly provided to the substrate, and a region lacking the embedded film 8 may be easily formed around the via hole 11, as shown in FIG. 5A. If CMP is performed under such a condition, the region lacking the embedded film 8 is polished faster than the other region having embedded film 8 thereon to give rise to a deeply and non-uniformly polished region 10 as shown in FIG. 5B. Thereby, an undesirable phenomenon is caused that the polishing develops to undesirably reach the lower wiring layer 2 around the via hole 11 as shown in FIG. 5B. When the upper electrode 9 is formed under such a condition shown in FIG. 5B, the lower wiring layer 2 and the upper electrode 9 may short out as shown in FIG. 5C. Accordingly, the via hole filled with CNTs 7 does not serve as wiring any more.
As described above, SOG is applied to the substrate having the interlayer insulating film 3 including the via hole filled with CNTs 7 therein, but is often applied not uniformly. Therefore, a region without uniform coating of SOG often appears as shown in FIG. 5A. The field region is also exposed to plasma when growing CNTs 7. The plasma is considered to chemically modify the surface of the region or to change the surface shape of the region. Such a surface of the field region undergoes CMP to be polished non-uniformly as shown in FIG. 5B. As a result, the interlayer insulating film 3 is locally polished, thereby causing an unintended hole to be formed around CNTs 7. An upper electrode is formed on the surface of the field region mentioned above to likely cause the upper electrode and the lower layer wiring 2 to short out. Under such a condition, the CNT via wiring does not serve as wiring any more.